[all-commits] [llvm/llvm-project] 932841: [mlir][vector] Fix TransferOpReduceRank for 0-D te...

[Lei Zhang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 93284120f28c82503138f3e594358349ed0ab37f
      https://github.com/llvm/llvm-project/commit/93284120f28c82503138f3e594358349ed0ab37f
  Author: Lei Zhang <antiagainst at google.com>
  Date:   2021-11-22 (Mon, 22 Nov 2021)

  Changed paths:
    M mlir/lib/Dialect/Vector/VectorTransferPermutationMapRewritePatterns.cpp
    M mlir/test/Dialect/Vector/vector-transfer-to-vector-load-store.mlir

  Log Message:
  -----------
  [mlir][vector] Fix TransferOpReduceRank for 0-D tensors

We cannot unconditionally generate memref.load ops for such cases;
need to check the source's type.

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D114376