[all-commits] [llvm/llvm-project] 137d34: [RISCV] Reverse the order of loading/storing calle...

[Kai Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 137d3474ca39a9af6130519a41b62dd58672a5c0
      https://github.com/llvm/llvm-project/commit/137d3474ca39a9af6130519a41b62dd58672a5c0
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-11-22 (Mon, 22 Nov 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
    M llvm/test/CodeGen/RISCV/aext-to-sext.ll
    M llvm/test/CodeGen/RISCV/alloca.ll
    M llvm/test/CodeGen/RISCV/atomic-rmw.ll
    M llvm/test/CodeGen/RISCV/atomic-signext.ll
    M llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
    M llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
    M llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
    M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
    M llvm/test/CodeGen/RISCV/calling-conv-half.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
    M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll
    M llvm/test/CodeGen/RISCV/calling-conv-lp64.ll
    M llvm/test/CodeGen/RISCV/calls.ll
    M llvm/test/CodeGen/RISCV/copysign-casts.ll
    M llvm/test/CodeGen/RISCV/double-arith.ll
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/double-fcmp.ll
    M llvm/test/CodeGen/RISCV/double-intrinsics.ll
    M llvm/test/CodeGen/RISCV/exception-pointer-register.ll
    M llvm/test/CodeGen/RISCV/fastcc-int.ll
    M llvm/test/CodeGen/RISCV/float-arith.ll
    M llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
    M llvm/test/CodeGen/RISCV/float-br-fcmp.ll
    M llvm/test/CodeGen/RISCV/float-convert.ll
    M llvm/test/CodeGen/RISCV/float-fcmp.ll
    M llvm/test/CodeGen/RISCV/float-intrinsics.ll
    M llvm/test/CodeGen/RISCV/fp16-promote.ll
    M llvm/test/CodeGen/RISCV/frame-info.ll
    M llvm/test/CodeGen/RISCV/frame.ll
    M llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll
    M llvm/test/CodeGen/RISCV/half-arith.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll
    M llvm/test/CodeGen/RISCV/half-intrinsics.ll
    M llvm/test/CodeGen/RISCV/half-mem.ll
    M llvm/test/CodeGen/RISCV/interrupt-attr-callee.ll
    M llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
    M llvm/test/CodeGen/RISCV/interrupt-attr.ll
    M llvm/test/CodeGen/RISCV/large-stack.ll
    M llvm/test/CodeGen/RISCV/mul.ll
    M llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir
    M llvm/test/CodeGen/RISCV/remat.ll
    M llvm/test/CodeGen/RISCV/rv32i-rv64i-float-double.ll
    M llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll
    M llvm/test/CodeGen/RISCV/rv32zbb.ll
    M llvm/test/CodeGen/RISCV/rv64i-complex-float.ll
    M llvm/test/CodeGen/RISCV/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
    M llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
    M llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
    M llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
    M llvm/test/CodeGen/RISCV/rvv/localvar.ll
    M llvm/test/CodeGen/RISCV/rvv/memory-args.ll
    M llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
    M llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
    M llvm/test/CodeGen/RISCV/select-cc.ll
    M llvm/test/CodeGen/RISCV/shadowcallstack.ll
    M llvm/test/CodeGen/RISCV/shifts.ll
    M llvm/test/CodeGen/RISCV/shrinkwrap.ll
    M llvm/test/CodeGen/RISCV/srem-lkk.ll
    M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
    M llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll
    M llvm/test/CodeGen/RISCV/stack-realignment.ll
    M llvm/test/CodeGen/RISCV/stack-store-check.ll
    M llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
    M llvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll
    M llvm/test/CodeGen/RISCV/urem-lkk.ll
    M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
    M llvm/test/CodeGen/RISCV/vararg.ll
    M llvm/test/CodeGen/RISCV/xaluo.ll

  Log Message:
  -----------
  [RISCV] Reverse the order of loading/storing callee-saved registers.

Currently, we restore the return address register as the last restoring
instruction in the epilog. The next instruction is `ret` usually. It is
a use of return address register. In some microarchitectures, there is
load-to-use data hazard. To avoid the load-to-use data hazard, we could
separate the load instruction from its use as far as possible. In this
patch, we reverse the order of restoring callee-saved registers to
increase the distance of `load ra` and `ret` in the epilog.

Differential Revision: https://reviews.llvm.org/D113967