[all-commits] [llvm/llvm-project] 7c5ecc: [mlir][vector] Insert/extract element can accept i...

[Jeff Niu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7c5ecc8b7e1bcd1b02eafeba9bbf3d5bc50d72c5
      https://github.com/llvm/llvm-project/commit/7c5ecc8b7e1bcd1b02eafeba9bbf3d5bc50d72c5
  Author: Mogball <jeffniu22 at gmail.com>
  Date:   2021-11-18 (Thu, 18 Nov 2021)

  Changed paths:
    M mlir/include/mlir/Dialect/Vector/VectorOps.td
    M mlir/include/mlir/IR/OpBase.td
    M mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp
    M mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
    M mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp
    M mlir/lib/Dialect/Vector/VectorMultiDimReductionTransforms.cpp
    M mlir/lib/Dialect/Vector/VectorOps.cpp
    M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
    M mlir/test/Conversion/VectorToSCF/vector-to-scf.mlir
    M mlir/test/Conversion/VectorToSPIRV/simple.mlir
    M mlir/test/Dialect/SparseTensor/sparse_vector.mlir
    M mlir/test/Dialect/SparseTensor/sparse_vector_chain.mlir
    M mlir/test/Dialect/Vector/vector-multi-reduction-lowering.mlir

  Log Message:
  -----------
  [mlir][vector] Insert/extract element can accept index

`vector::InsertElementOp` and `vector::ExtractElementOp` have had their `position`
operand changed to accept `AnySignlessIntegerOrIndex` for better operability with
operations that use `index`, such as affine loops.

LLVM's `extractelement` and `insertelement` can also accept `i64`, so lowering
directly to these operations without explicitly inserting casts is allowed. SPIRV's
equivalent ops can also accept `i64`.

Reviewed By: nicolasvasilache, jpienaar

Differential Revision: https://reviews.llvm.org/D114139