[all-commits] [llvm/llvm-project] 24d167: [llvm-tblgen][RISCV] Make llvm-tblgen RISCVCompres...

[Zi Xuan Wu (Zeson) via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 24d1673c8b9ba32083ad3fa8d587a9fab8b637ad
      https://github.com/llvm/llvm-project/commit/24d1673c8b9ba32083ad3fa8d587a9fab8b637ad
  Author: Zi Xuan Wu <zixuan.wu at linux.alibaba.com>
  Date:   2021-11-18 (Thu, 18 Nov 2021)

  Changed paths:
    M llvm/include/llvm/Target/Target.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
    M llvm/test/TableGen/AsmPredicateCombiningRISCV.td
    M llvm/utils/TableGen/CMakeLists.txt
    A llvm/utils/TableGen/CompressInstEmitter.cpp
    R llvm/utils/TableGen/RISCVCompressInstEmitter.cpp

  Log Message:
  -----------
  [llvm-tblgen][RISCV] Make llvm-tblgen RISCVCompressInstEmitter to be common infra across different targets

Not only RISCV but also other target such as CSKY, there are compressed instructions mixed with normal instructions.
To reuse the basic infra to compress/uncompress and predict instruction, we need reconstruct the RISCVCompressInstEmitter
and make it more general and suitable for other target.

Differential Revision: https://reviews.llvm.org/D113475