[all-commits] [llvm/llvm-project] aeb3c7: [X86] Add shift by splat modulo amount vector tests

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: aeb3c772d316ed71836bccf515517e769150e6a1
      https://github.com/llvm/llvm-project/commit/aeb3c772d316ed71836bccf515517e769150e6a1
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2021-11-16 (Tue, 16 Nov 2021)

  Changed paths:
    M llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
    M llvm/test/CodeGen/X86/vector-shift-ashr-256.ll
    M llvm/test/CodeGen/X86/vector-shift-ashr-512.ll
    M llvm/test/CodeGen/X86/vector-shift-lshr-128.ll
    M llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
    M llvm/test/CodeGen/X86/vector-shift-lshr-512.ll
    M llvm/test/CodeGen/X86/vector-shift-shl-128.ll
    M llvm/test/CodeGen/X86/vector-shift-shl-256.ll
    M llvm/test/CodeGen/X86/vector-shift-shl-512.ll

  Log Message:
  -----------
  [X86] Add shift by splat modulo amount vector tests

Shows failure to fold zero_extend_vector_inreg(and(x, c)) -> bitcast(and(x,c')) when we're only demanding the 0'th extended element, such as with the SSE variable shift ops.