[all-commits] [llvm/llvm-project] 460745: [AArch64] Fix TypeSize->uint64_t implicit conversi...

[david-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 460745902275c341889bde9daeb41287359e59e3
      https://github.com/llvm/llvm-project/commit/460745902275c341889bde9daeb41287359e59e3
  Author: David Sherwood <david.sherwood at arm.com>
  Date:   2021-11-16 (Tue, 16 Nov 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/test/CodeGen/AArch64/vselect-constants.ll

  Log Message:
  -----------
  [AArch64] Fix TypeSize->uint64_t implicit conversion in AArch64ISelLowering::hasAndNot

For now I've just changed the code to only return true from
AArch64ISelLowering::hasAndNot if the vector is fixed-length.
Once we have the right patterns or DAG combines to use bic/bif
we can also enable this for SVE.

Test added here:

  CodeGen/AArch64/vselect-constants.ll

Differential Revision: https://reviews.llvm.org/D113994