[all-commits] [llvm/llvm-project] f526c6: [AArch64][SVE] Instcombine SVE LD1/ST1 to stock LL...

[Matthew Devereau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f526c600c043d9e83a359e79d617077d947c1dc3
      https://github.com/llvm/llvm-project/commit/f526c600c043d9e83a359e79d617077d947c1dc3
  Author: Matt Devereau <matthew.devereau at arm.com>
  Date:   2021-11-16 (Tue, 16 Nov 2021)

  Changed paths:
    M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1-bfloat.c
    M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1.c
    M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sb.c
    M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sh.c
    M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sw.c
    M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ub.c
    M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uh.c
    M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uw.c
    M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1-bfloat.c
    M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1.c
    M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1b.c
    M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1h.c
    M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1w.c
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
    A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-loadstore.ll

  Log Message:
  -----------
  [AArch64][SVE] Instcombine SVE LD1/ST1 to stock LLVM IR

InstCombine AArch64 LD1/ST1 to llvm.masked.load/llvm.masked.store
and LD1/ST1 to load/store when a ptrue all predicate pattern operand
is present.

This allows existing IR optimizations such as dead-load removal to
occur.

Differential Revision: https://reviews.llvm.org/D113489