[all-commits] [llvm/llvm-project] d90eea: [RISCV] Add test cases to prepare for overring Tar...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d90eeab0ed1d73d1db62edf9b49527f3b3e4140c
      https://github.com/llvm/llvm-project/commit/d90eeab0ed1d73d1db62edf9b49527f3b3e4140c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-11-15 (Mon, 15 Nov 2021)

  Changed paths:
    A llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
    A llvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll

  Log Message:
  -----------
  [RISCV] Add test cases to prepare for overring TargetLowering::hasAndNot. NFC

These test files are copied directly from AArch64. Some of the cases
may benefit from ANDN with the Zbb extension. Somes cases already
improve use ANDN.

selectcc-to-shiftand.ll also contains tests that test select->and
conversion even when a ANDN isn't needed. I think this improves our
coverage of these optimizations.

Differential Revision: https://reviews.llvm.org/D113935


  Commit: 391b0ba603ab4e2b5fcdfe29a2907a67831293df
      https://github.com/llvm/llvm-project/commit/391b0ba603ab4e2b5fcdfe29a2907a67831293df
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-11-15 (Mon, 15 Nov 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
    M llvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll

  Log Message:
  -----------
  [RISCV] Override TargetLowering::hasAndNot for Zbb.

Differential Revision: https://reviews.llvm.org/D113937


Compare: https://github.com/llvm/llvm-project/compare/b484fa828929...391b0ba603ab