[all-commits] [llvm/llvm-project] e6bfbd: AMDGPU: Regenerate test checks
Matt Arsenault via All-commits
all-commits at lists.llvm.org
Mon Nov 15 18:35:20 PST 2021
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: e6bfbd7e0dc41d394d4eee69f727660090eaf828
https://github.com/llvm/llvm-project/commit/e6bfbd7e0dc41d394d4eee69f727660090eaf828
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2021-11-15 (Mon, 15 Nov 2021)
Changed paths:
M llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir
M llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
M llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
Log Message:
-----------
AMDGPU: Regenerate test checks
Commit: 659887b4056236d376c0ac1218ca3f7a0dd75604
https://github.com/llvm/llvm-project/commit/659887b4056236d376c0ac1218ca3f7a0dd75604
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2021-11-15 (Mon, 15 Nov 2021)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/lds-atomic-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir
M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir
M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir
M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir
M llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
M llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
M llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
Log Message:
-----------
AMDGPU: Mark prolog/epilog SCC defs as dead
A future change will add SCC liveness checks. Since we are still
relying on forward register scavenging, add dead flags to avoid
spuriously detecting SCC as live.
Compare: https://github.com/llvm/llvm-project/compare/17194ca96ab5...659887b40562
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