[all-commits] [llvm/llvm-project] 02bed6: [RISCV] Improve codegen for i32 udiv/urem by const...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 02bed66cd5923a9964b7cb2211eae4bf3a065c6f
      https://github.com/llvm/llvm-project/commit/02bed66cd5923a9964b7cb2211eae4bf3a065c6f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-11-12 (Fri, 12 Nov 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoM.td
    M llvm/test/CodeGen/RISCV/div.ll
    M llvm/test/CodeGen/RISCV/urem-lkk.ll

  Log Message:
  -----------
  [RISCV] Improve codegen for i32 udiv/urem by constant on RV64.

The division by constant optimization often produces constants that
are uimm32, but not simm32. These constants require 3 or 4 instructions
to materialize without Zba.

Since these instructions are often used by a multiply with a LHS
that needs to be zero extended with an AND, we can switch the MUL
to a MULHU by shifting both inputs left by 32. Once we shift the
constant left, the upper 32 bits no longer need to be 0 so constant
materialization is free to use LUI+ADDIW. This reduces the constant
materialization from 4 instructions to 3 in some cases while also
reducing the zero extend of the LHS from 2 shifts to 1.

Differential Revision: https://reviews.llvm.org/D113805