[all-commits] [llvm/llvm-project] 764782: [AArch64][SVE] Remove i1 type from isElementTypeLe...

[kmclaughlin-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 76478221565167da286bdc2d6a13eb241563e31c
      https://github.com/llvm/llvm-project/commit/76478221565167da286bdc2d6a13eb241563e31c
  Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
  Date:   2021-11-12 (Fri, 12 Nov 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-illegal-type.ll

  Log Message:
  -----------
  [AArch64][SVE] Remove i1 type from isElementTypeLegalForScalableVector

`collectElementTypesForWidening` collects the types of load, store and
reduction Phis in a loop. These types are later checked using
`isElementTypeLegalForScalableVector` to prevent vectorisation of
loops with instruction types that are unsupported.

This patch removes i1 from the list of types supported for scalable
vectors. This fixes an assert ("Cannot yet scalarize uniform stores") in
`setCostBasedWideningDecision` when we have a loop containing a uniform
i1 store and a scalable VF, which we cannot create a scatter for.

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D113680