[all-commits] [llvm/llvm-project] ee7a00: [RISCV] Promote f16 ceil/floor/round/roundeven/nea...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ee7a006ce461740ea2aeb2c17d80a0ff7667f603
      https://github.com/llvm/llvm-project/commit/ee7a006ce461740ea2aeb2c17d80a0ff7667f603
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-11-11 (Thu, 11 Nov 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/half-intrinsics.ll

  Log Message:
  -----------
  [RISCV] Promote f16 ceil/floor/round/roundeven/nearbyint/rint/trunc intrinsics to f32 libcalls.

Previously these would crash. I don't think these can be generated
directly from C. Not sure if any optimizations can introduce them.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D113527