[all-commits] [llvm/llvm-project] 11522c: [DAGCombiner] add fold for vselect based on mask o...

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  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 11522cfcad6ba38b0b61a727a711adeef98571c9
      https://github.com/llvm/llvm-project/commit/11522cfcad6ba38b0b61a727a711adeef98571c9
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2021-11-11 (Thu, 11 Nov 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AArch64/vselect-constants.ll
    M llvm/test/CodeGen/X86/vselect-zero.ll

  Log Message:
  -----------
  [DAGCombiner] add fold for vselect based on mask of signbit, part 3

(Cond0 s> -1) ? N1 : 0 --> ~(Cond0 s>> BW-1) & N1

https://alive2.llvm.org/ce/z/mGCBrd

This was suggested as a potential enhancement in D113212 (also 7e30404c3b6c ).
There's an improvement for AArch that could be generalized ( X > -1 --> X >= 0 ).
For x86, we have a counter-acting fold for most cases that turns the shift+not
back into a setcc, so that needs a work-around to get more cases to use "pandn":
D113603

Note that this pattern (and a previous one) are not currently canonical forms
in IR:
https://alive2.llvm.org/ce/z/e4o96b

Adding swapped variants is left as a TODO item here, but is planned as
a near-term follow-up patch.

Differential Revision: https://reviews.llvm.org/D113426