[all-commits] [llvm/llvm-project] 418352: [RISCV] Promote f16 frem with Zfh.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4183522e80733d40865d0f379a6fb30a0fd8e052
      https://github.com/llvm/llvm-project/commit/4183522e80733d40865d0f379a6fb30a0fd8e052
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-11-10 (Wed, 10 Nov 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/double-frem.ll
    M llvm/test/CodeGen/RISCV/float-frem.ll
    A llvm/test/CodeGen/RISCV/half-frem.ll

  Log Message:
  -----------
  [RISCV] Promote f16 frem with Zfh.

Add riscv64 coverage for f32 and f64 frem.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D113531