[all-commits] [llvm/llvm-project] 2d99c8: [mlir-tblgen] Support `either` in Tablegen DRR.

[ChiaHungDuan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2d99c815d7c2f40d9be1270b276768374291b68e
      https://github.com/llvm/llvm-project/commit/2d99c815d7c2f40d9be1270b276768374291b68e
  Author: Chia-hung Duan <chiahungduan at google.com>
  Date:   2021-11-08 (Mon, 08 Nov 2021)

  Changed paths:
    M mlir/docs/DeclarativeRewrites.md
    M mlir/include/mlir/IR/OpBase.td
    M mlir/include/mlir/TableGen/Pattern.h
    M mlir/lib/TableGen/Pattern.cpp
    M mlir/test/lib/Dialect/Test/TestOps.td
    M mlir/test/mlir-tblgen/pattern.mlir
    M mlir/tools/mlir-tblgen/RewriterGen.cpp

  Log Message:
  -----------
  [mlir-tblgen] Support `either` in Tablegen DRR.

Add a new directive `either` to specify the operands can be matched in either order

Reviewed By: jpienaar, Mogball

Differential Revision: https://reviews.llvm.org/D110666