[all-commits] [llvm/llvm-project] 05f64b: [InstCombine] add signbit tests for icmp with trun...

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  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 05f64b5ac972010b386f09ccb19a13c5c42c5880
      https://github.com/llvm/llvm-project/commit/05f64b5ac972010b386f09ccb19a13c5c42c5880
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2021-11-05 (Fri, 05 Nov 2021)

  Changed paths:
    M llvm/test/Transforms/InstCombine/icmp-trunc.ll

  Log Message:
  -----------
  [InstCombine] add signbit tests for icmp with trunc; NFC


  Commit: 8918814032276acef921f35bb73070ff277e310f
      https://github.com/llvm/llvm-project/commit/8918814032276acef921f35bb73070ff277e310f
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2021-11-05 (Fri, 05 Nov 2021)

  Changed paths:
    M llvm/test/CodeGen/X86/vselect-zero.ll

  Log Message:
  -----------
  [x86] add tests for vector select; NFC


  Commit: 1e7afa2a0dd76af177f23695c69892764f33534e
      https://github.com/llvm/llvm-project/commit/1e7afa2a0dd76af177f23695c69892764f33534e
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2021-11-05 (Fri, 05 Nov 2021)

  Changed paths:
    M llvm/test/CodeGen/AArch64/vselect-constants.ll

  Log Message:
  -----------
  [AArch64] add tests for vector select; NFC


  Commit: 4fc1fc4005f7818e1f8a795ca15ca8f8c03e426a
      https://github.com/llvm/llvm-project/commit/4fc1fc4005f7818e1f8a795ca15ca8f8c03e426a
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2021-11-05 (Fri, 05 Nov 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AArch64/vselect-constants.ll
    M llvm/test/CodeGen/Thumb2/mve-vselect-constants.ll
    M llvm/test/CodeGen/X86/avx512-logic.ll
    M llvm/test/CodeGen/X86/avx512vl-logic.ll
    M llvm/test/CodeGen/X86/vselect-zero.ll

  Log Message:
  -----------
  [DAGCombiner] add fold for vselect based on mask of signbit

(X s< 0) ? Y : 0 --> (X s>> BW-1) & Y

We canonicalize to the icmp+select form in IR, and we already have this fold
for scalar select in SDAG, so I think it's an oversight that we don't have
the fold for vectors. It seems neutral for AArch64 and saves some instructions
on x86.

Whether we should also have the sibling folds for the inverse condition or
all-ones true value may depend on target-specific factors such as whether
there's an "and-not" instruction.

Differential Revision: https://reviews.llvm.org/D113212


Compare: https://github.com/llvm/llvm-project/compare/6cd309bd02c3...4fc1fc4005f7