[all-commits] [llvm/llvm-project] 657a1d: [AArch64] Add target DAG combine for UUNPKHI/LO

[david-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 657a1dcd0dca73cffc5c6011d4a1ce63313fa2ae
      https://github.com/llvm/llvm-project/commit/657a1dcd0dca73cffc5c6011d4a1ce63313fa2ae
  Author: David Sherwood <david.sherwood at arm.com>
  Date:   2021-11-05 (Fri, 05 Nov 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/sve-insert-vector.ll

  Log Message:
  -----------
  [AArch64] Add target DAG combine for UUNPKHI/LO

When created a UUNPKLO/HI node with an undef input then the
output should also be undef. I've added a target DAG combine
function to ensure we avoid creating an unnecessary uunpklo/hi
instruction.

Differential Revision: https://reviews.llvm.org/D113266