[all-commits] [llvm/llvm-project] ec0e1e: [TwoAddressInstructionPass] Update existing physre...

[Jay Foad via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ec0e1e88d24fadb2cb22f431d66b22ee1b01cd43
      https://github.com/llvm/llvm-project/commit/ec0e1e88d24fadb2cb22f431d66b22ee1b01cd43
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2021-11-05 (Fri, 05 Nov 2021)

  Changed paths:
    M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
    M llvm/test/CodeGen/ARM/inlineasm-operand-implicit-cast.ll
    M llvm/test/CodeGen/Thumb/emergency-spill-slot.ll
    M llvm/test/CodeGen/X86/inline-asm-A-constraint.ll

  Log Message:
  -----------
  [TwoAddressInstructionPass] Update existing physreg live intervals

In TwoAddressInstructionPass::processTiedPairs with
-early-live-intervals, update any preexisting physreg live intervals,
as well as virtreg live intervals. By default (without
-precompute-phys-liveness) physreg live intervals only exist for
registers that are live-in to some basic block.

Differential Revision: https://reviews.llvm.org/D113191


  Commit: c93bf53a3ecb57f3077d5cbf0d797a88fb2d1b44
      https://github.com/llvm/llvm-project/commit/c93bf53a3ecb57f3077d5cbf0d797a88fb2d1b44
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2021-11-05 (Fri, 05 Nov 2021)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp

  Log Message:
  -----------
  [AMDGPU] NFC formatting fixes in SIMemoryLegalizer


Compare: https://github.com/llvm/llvm-project/compare/020ca1747d6c...c93bf53a3ecb