[all-commits] [llvm/llvm-project] 3bc586: [ARM] Treat MVE gather add-like-or's like adds

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3bc586b9aa6f33e8acdea0fa80362879f26a8be7
      https://github.com/llvm/llvm-project/commit/3bc586b9aa6f33e8acdea0fa80362879f26a8be7
  Author: David Green <david.green at arm.com>
  Date:   2021-11-03 (Wed, 03 Nov 2021)

  Changed paths:
    M llvm/lib/Target/ARM/MVEGatherScatterLowering.cpp
    M llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
    M llvm/test/CodeGen/Thumb2/mve-scatter-increment.ll

  Log Message:
  -----------
  [ARM] Treat MVE gather add-like-or's like adds

LLVM has the habit of turning adds with no common bits set into ors,
which means we need to detect them and treat them like adds again in the
MVE gather/scatter lowering pass.

Differential Revision: https://reviews.llvm.org/D112922