[all-commits] [llvm/llvm-project] a39ead: [DAGCombiner] Teach combineShiftToMULH to handle c...

[Jianjian Guan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a39eadcf1609db66a42fa00d55da6e1ff734e1b3
      https://github.com/llvm/llvm-project/commit/a39eadcf1609db66a42fa00d55da6e1ff734e1b3
  Author: jacquesguan <jacquesguan at me.com>
  Date:   2021-11-02 (Tue, 02 Nov 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll

  Log Message:
  -----------
  [DAGCombiner] Teach combineShiftToMULH to handle constant and const splat vector.

Fold (srl (mul (zext i32:$a to i64), i64:c), 32) -> (mulhu $a, $b),
if c can truncate to i32 without loss.

Reviewed By: frasercrmck, craig.topper, RKSimon

Differential Revision: https://reviews.llvm.org/D108129