[all-commits] [llvm/llvm-project] aa2d3b: GlobalISel/Utils: Use incoming regbank while const...

[Christudasan Devadasan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: aa2d3b59ce75a5808f2fe3f2010920c1e19711bf
      https://github.com/llvm/llvm-project/commit/aa2d3b59ce75a5808f2fe3f2010920c1e19711bf
  Author: Christudasan Devadasan <Christudasan.Devadasan at amd.com>
  Date:   2021-10-30 (Sat, 30 Oct 2021)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/Utils.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir

  Log Message:
  -----------
  GlobalISel/Utils: Use incoming regbank while constraining the superclasses

Register operands with superclasses can possibly have multiple regBanks
if they have different register types. The regBank ambiguity resolved
during regbankselect should be used to constrain the operand regclass
instead of obtaining one from the MCInstrDesc.

This is a prerequisite patch for D109300 that introduces allocatable AV_*
Superclasses for AMDGPU by combining both VGPRs and AGPRs and we want to
restrain the regclass to either A or V based on the incoming regbank.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D112323