[all-commits] [llvm/llvm-project] aefcd5: [RISCV] Teach RISCVInsertVSETVLI::needVSETVLI to h...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: aefcd598959abbea5eddf1fe454359f53bd9d853
      https://github.com/llvm/llvm-project/commit/aefcd598959abbea5eddf1fe454359f53bd9d853
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-10-29 (Fri, 29 Oct 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

  Log Message:
  -----------
  [RISCV] Teach RISCVInsertVSETVLI::needVSETVLI to handle mask register instructions better.

If the VL operand of a mask register instruction comes from an
explicit vsetvli with a different VTYPE, we can still avoid needing
a vsetvli as long as the SEW/LMUL ratio is the same and policy bits
match.

Differential Revision: https://reviews.llvm.org/D112762