[all-commits] [llvm/llvm-project] 13faa5: [AArch64][SVE] Generate SVE >1 element structured ...

[Bradley Smith via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 13faa5f44015e111e938f301d40478d965567a5d
      https://github.com/llvm/llvm-project/commit/13faa5f44015e111e938f301d40478d965567a5d
  Author: Bradley Smith <bradley.smith at arm.com>
  Date:   2021-10-29 (Fri, 29 Oct 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
    A llvm/test/Transforms/InterleavedAccess/AArch64/sve-interleaved-accesses.ll

  Log Message:
  -----------
  [AArch64][SVE] Generate SVE >1 element structured load/stores from fixed types

This adds support for SVE structured loads/stores to the relevant target
hooks, such that we can support these instructions in the InterleavedAccess
pass.

Depends on D112078

Differential Revision: https://reviews.llvm.org/D112303