[all-commits] [llvm/llvm-project] 67c44a: [RISCV] Add a test case showing unnecessary vsetvl...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 67c44a997854c3b95e84f1f817c0eeac61fddc1b
      https://github.com/llvm/llvm-project/commit/67c44a997854c3b95e84f1f817c0eeac61fddc1b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-10-28 (Thu, 28 Oct 2021)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

  Log Message:
  -----------
  [RISCV] Add a test case showing unnecessary vsetvli for mask register instructions.

If the VL argument for a mask instruction comes from a vsetvli with
an SEW!=8, we will insert an extra vsetvli for the mask instruction
even if the SEW/LMUL ratio is the same. This requires at least one
instruction before the mask instruction that needs the SEW of the
explicit vsetvli. Otherwise, we'll just rewrite the explicit vsetvli.