[all-commits] [llvm/llvm-project] e6a4ba: [amdgpu] Handle the case where there is no scaveng...
darkbuck via All-commits
all-commits at lists.llvm.org
Wed Oct 27 15:37:48 PDT 2021
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: e6a4ba3aa603e542e6e0f7f7d9aca3cfa7c3f03f
https://github.com/llvm/llvm-project/commit/e6a4ba3aa603e542e6e0f7f7d9aca3cfa7c3f03f
Author: Michael Liao <michael.hliao at gmail.com>
Date: 2021-10-27 (Wed, 27 Oct 2021)
Changed paths:
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/lib/CodeGen/BranchRelaxation.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
M llvm/lib/Target/AVR/AVRInstrInfo.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
Log Message:
-----------
[amdgpu] Handle the case where there is no scavenged register.
- When an unconditional branch is expanded into an indirect branch, if
there is no scavenged register, an SGPR pair needs spilling to enable
the destination PC calculation. In addition, before jumping into the
destination, that clobbered SGPR pair need restoring.
- As SGPR cannot be spilled to or restored from memory directly, the
spilling/restoring of that SGPR pair reuses the regular SGPR spilling
support but without spilling it into memory. As that spilling and
restoring points are fully controlled, we only need to spill that SGPR
into the temporary VGPR, which needs spilling into its emergency slot.
- The target-specific hook is revised to take additional restore block,
where the restoring code is filled. After that, the relaxation will
place that restore block directly before the destination block and
insert an unconditional branch in any fall-through block into the
destination block.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D106449
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