[all-commits] [llvm/llvm-project] fc28a2: [AArch64][SVE] Combine predicated FMUL/FADD into FMA

[Matthew Devereau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fc28a2f8ced4ff3565f2c47fead824a017c25d21
      https://github.com/llvm/llvm-project/commit/fc28a2f8ced4ff3565f2c47fead824a017c25d21
  Author: Matt <matthew.devereau at arm.com>
  Date:   2021-10-27 (Wed, 27 Oct 2021)

  Changed paths:
    M llvm/include/llvm/IR/Operator.h
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
    A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-fmla.ll

  Log Message:
  -----------
  [AArch64][SVE] Combine predicated FMUL/FADD into FMA

Combine FADD and FMUL intrinsics into FMA when the result of the FMUL is an FADD operand
with one only use and both use the same predicate.

Differential Revision: https://reviews.llvm.org/D111638