[all-commits] [llvm/llvm-project] 6e46b6: [DAGCombiner] make matching bit-hack form of usubs...

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  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6e46b66e2aa7ccfc65d26d1a640e0365a2bdae02
      https://github.com/llvm/llvm-project/commit/6e46b66e2aa7ccfc65d26d1a640e0365a2bdae02
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2021-10-25 (Mon, 25 Oct 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AMDGPU/usubsat.ll
    M llvm/test/CodeGen/X86/psubus.ll

  Log Message:
  -----------
  [DAGCombiner] make matching bit-hack form of usubsat more flexible

(i8 X ^ 128) & (i8 X s>> 7) --> usubsat X, 128

As suggested in D112085, we can substitute 'xor' with 'add'
in this pattern, and it is logically equivalent:
https://alive2.llvm.org/ce/z/eJtWWC

We canonicalize to 'xor' in IR, but SDAG does not do that
(and it probably should not - https://llvm.org/PR52267 ), so
it is possible to see either pattern in codegen. Note that
'sub' is a another potential pattern, but that is
canonicalized to 'add' in DAGCombiner, so we don't need to
worry about that variation.

Differential Revision: https://reviews.llvm.org/D112377