[all-commits] [llvm/llvm-project] 0ce46a: [AArch64][Driver][SVE] Allow -msve-vector-bits=<n>...

[Bradley Smith via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0ce46a1d43c6c2e0df429a6a80848d4acc781eb6
      https://github.com/llvm/llvm-project/commit/0ce46a1d43c6c2e0df429a6a80848d4acc781eb6
  Author: Bradley Smith <bradley.smith at arm.com>
  Date:   2021-10-25 (Mon, 25 Oct 2021)

  Changed paths:
    M clang/include/clang/Basic/LangOptions.def
    M clang/include/clang/Driver/Options.td
    M clang/lib/AST/ASTContext.cpp
    M clang/lib/Basic/Targets/AArch64.cpp
    M clang/lib/Driver/ToolChains/Clang.cpp
    M clang/lib/Sema/SemaType.cpp
    M clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
    M clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp
    M clang/test/CodeGen/aarch64-sve-vector-bits-codegen.c
    M clang/test/CodeGen/arm-sve-vector-bits-vscale-range.c
    M clang/test/CodeGen/attr-arm-sve-vector-bits-bitcast.c
    M clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
    M clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
    M clang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c
    M clang/test/CodeGen/attr-arm-sve-vector-bits-globals.c
    M clang/test/CodeGen/attr-arm-sve-vector-bits-types.c
    M clang/test/CodeGenCXX/aarch64-mangle-sve-fixed-vectors.cpp
    M clang/test/CodeGenCXX/aarch64-sve-fixedtypeinfo.cpp
    M clang/test/Driver/aarch64-sve-vector-bits.c
    M clang/test/Preprocessor/aarch64-target-features.c
    M clang/test/Sema/aarch64-sve-explicit-casts-fixed-size.c
    M clang/test/Sema/aarch64-sve-lax-vector-conversions.c
    M clang/test/Sema/attr-arm-sve-vector-bits.c
    M clang/test/SemaCXX/aarch64-sve-explicit-casts-fixed-size.cpp
    M clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
    M clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp

  Log Message:
  -----------
  [AArch64][Driver][SVE] Allow -msve-vector-bits=<n>+ syntax to mean no maximum vscale

This patch splits the existing SveVectorBits LangOpt into VScaleMin and
VScaleMax LangOpts such that we can represent such an option. The cc1
option has also been split into -mvscale-{min,max}=<n> options so that the
cc1 arguments better reflect the vscale_range IR attribute.

Differential Revision: https://reviews.llvm.org/D111790