[all-commits] [llvm/llvm-project] a50243: [AArch64] Remove redundant ORRWrs which is generat...

[JinGu Kang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a502436259307f95e9c95437d8a1d2d07294341c
      https://github.com/llvm/llvm-project/commit/a502436259307f95e9c95437d8a1d2d07294341c
  Author: Jingu Kang <jingu.kang at arm.com>
  Date:   2021-10-25 (Mon, 25 Oct 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
    M llvm/test/CodeGen/AArch64/arm64-assert-zext-sext.ll
    A llvm/test/CodeGen/AArch64/redundant-mov-from-zero-extend.ll
    A llvm/test/CodeGen/AArch64/redundant-orrwrs-from-zero-extend.mir

  Log Message:
  -----------
  [AArch64] Remove redundant ORRWrs which is generated by zero-extend

%3:gpr32 = ORRWrs $wzr, %2, 0
%4:gpr64 = SUBREG_TO_REG 0, %3, %subreg.sub_32

If AArch64's 32-bit form of instruction defines the source operand of ORRWrs,
we can remove the ORRWrs because the upper 32 bits of the source operand are
set to zero.

Differential Revision: https://reviews.llvm.org/D110841