[all-commits] [llvm/llvm-project] ff37b1: [LegalizeVectorOps][X86] Don't defer BITREVERSE ex...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ff37b1105d6eb7b9a4e4515c2ced95e9837567aa
      https://github.com/llvm/llvm-project/commit/ff37b1105d6eb7b9a4e4515c2ced95e9837567aa
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
    M llvm/test/CodeGen/X86/bitreverse.ll
    M llvm/test/CodeGen/X86/combine-bitreverse.ll
    M llvm/test/CodeGen/X86/vector-bitreverse.ll

  Log Message:
  -----------
  [LegalizeVectorOps][X86] Don't defer BITREVERSE expansion to LegalizeDAG.

By expanding early it allows the shifts to be custom lowered in
LegalizeVectorOps. Then a DAG combine is able to run on them before
LegalizeDAG handles the BUILD_VECTORS for the masks used.

v16Xi8 shift lowering on X86 requires a mask to be applied to a v8i16
shift. The BITREVERSE expansion applied an AND mask before SHL ops and
after SRL ops. This was done to share the same mask constant for both shifts.
It looks like this patch allows DAG combine to remove the AND mask added
after v16i8 SHL by X86 lowering. This maintains the mask sharing that
BITREVERSE was trying to achieve. Prior to this patch it looks like
we kept the mask after the SHL instead which required an extra constant
pool or a PANDN to invert it.

This is dependent on D112248 because RISCV will end up scalarizing the BSWAP
portion of the BITREVERSE expansion if we don't disable BSWAP scalarization in
LegalizeVectorOps first.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D112254