[all-commits] [llvm/llvm-project] 92673f: [RISCV] Add a test showing incorrect VSETVLI inser...

[Fraser Cormack via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 92673fad66f449f63acc76dfbb5e0bf05978663b
      https://github.com/llvm/llvm-project/commit/92673fad66f449f63acc76dfbb5e0bf05978663b
  Author: Fraser Cormack <fraser at codeplay.com>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir

  Log Message:
  -----------
  [RISCV] Add a test showing incorrect VSETVLI insertion

This test case, reduced from an internal test failure, shows how we may
incorrectly skip the insertion of VSETVLI instructions when doing
cross-basic-block analysis.

The entry block ends in a `e32,mf2`. Its single successor, %bb.1, ends with a
`e8,mf8`, but for a mask-type instruction, so is considered compatible.
This means that the info %bb.1 is merged into its predecessor so
produces a `e32,mf2`. When it comes to the last block, which requires a
`e32,mf2`, we skip the insertion of a vsetvli because all predecessors
were determined to preserve the right vtype.

However, when %bb.1 is actually laid out it does actually need a
`e8,mf8` vsetvli, since the previous instruction has a different tail
policy. This means that when execution flows from %bb.1 to %bb.3, the
`vadd.vx` is misconfigured.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D112223