[all-commits] [llvm/llvm-project] d21987: [DAGCombiner] fold bit-hack form of usubsat

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  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d2198771e9ccbae27a487cdca67720eee71cea2a
      https://github.com/llvm/llvm-project/commit/d2198771e9ccbae27a487cdca67720eee71cea2a
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AMDGPU/usubsat.ll
    M llvm/test/CodeGen/X86/psubus.ll

  Log Message:
  -----------
  [DAGCombiner] fold bit-hack form of usubsat

(i8 X ^ 128) & (i8 X s>> 7) --> usubsat X, 128

I haven't found a generalization of this identity:
https://alive2.llvm.org/ce/z/_sriEQ

Note: I was actually looking at the first form of the pattern in that link,
but that's part of a long chain of potential missed transforms in codegen
and IR....that I hope ends here!

The predicates for when this is profitable are a bit tricky. This version of
the patch excludes multi-use but includes custom lowering (as opposed to
legal only).

On x86 for example, we have custom lowering for some vector types, and that
uses umax and sub. So to enable that fold, we need add use checks to avoid
regressions. Even with legal-only lowering, we could see code with extra
reg move instructions for extra uses, so that constraint would have to be
eased very carefully to avoid penalties.

Differential Revision: https://reviews.llvm.org/D112085