[all-commits] [llvm/llvm-project] 80ab06: [InstCombine] fold fake vector insert to bit-logic

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  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 80ab06c599a0f5a90951c36a57b2a9b492b19d61
      https://github.com/llvm/llvm-project/commit/80ab06c599a0f5a90951c36a57b2a9b492b19d61
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2021-10-20 (Wed, 20 Oct 2021)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
    M llvm/test/Transforms/InstCombine/bitcast-inselt-bitcast.ll

  Log Message:
  -----------
  [InstCombine] fold fake vector insert to bit-logic

bitcast (inselt (bitcast X), Y, 0) --> or (and X, MaskC), (zext Y)

https://alive2.llvm.org/ce/z/Ux-662

Similar to D111082 / db231ebdb07f :
We want to avoid relatively opaque vector ops on types that are
likely supported by the backend as scalar integers. The bitwise
logic ops are more likely to allow further combining.

We probably want to generalize this to allow a shift too, but
that would oppose instcombine's general rule of not creating
extra instructions, so that's left as a potential follow-up.
Alternatively, we could do that transform in VectorCombine
with the help of the TTI cost model.

This is part of solving:
https://llvm.org/PR52057