[all-commits] [llvm/llvm-project] 84d9bc: [RISCV] Rewrite forwardCopyWillClobberTuple to not...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 84d9bc51a33bc4dfaab32473fe301170a984ca93
      https://github.com/llvm/llvm-project/commit/84d9bc51a33bc4dfaab32473fe301170a984ca93
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-10-18 (Mon, 18 Oct 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

  Log Message:
  -----------
  [RISCV] Rewrite forwardCopyWillClobberTuple to not assume that there are exactly 32 registers. NFC

This function was copied from ARM where register pairs/triples/quads can wrap around the 32 encoding space. So register 31 can pair with register 0. This is not true for RISCV vectors. The spec specifically mentions the possibility of a future encoding that has more than 32 registers.

This patch removes the modulo from the code and directly checks that destination register is in the source register range and not the beginning of the range. Though I don't expect an identity copy will occur.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D111467