[all-commits] [llvm/llvm-project] faa0e2: [SelectionDAG] Fix shift libcall ABI mismatch in s...

[nextsilicon-itay-bookstein via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: faa0e2ae7644c332180cfe4e19daf378bc7a46a9
      https://github.com/llvm/llvm-project/commit/faa0e2ae7644c332180cfe4e19daf378bc7a46a9
  Author: Itay Bookstein <itay.bookstein at nextsilicon.com>
  Date:   2021-10-08 (Fri, 08 Oct 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/test/CodeGen/AArch64/shift_minsize.ll
    M llvm/test/CodeGen/RISCV/shifts.ll
    M llvm/test/CodeGen/X86/shift_minsize.ll

  Log Message:
  -----------
  [SelectionDAG] Fix shift libcall ABI mismatch in shift-amount argument

The shift libcalls have a shift amount parameter of MVT::i32, but
sometimes ExpandIntRes_Shift may be called with a node whose
second operand is a type that is larger than that. This leads to
an ABI mismatch, and for example causes a spurious zeroing of
a register in RV32 for 64-bit shifts. Note that at present regular
shift intstructions already have their shift amount operand adapted
at SelectionDAGBuilder::visitShift time, and funnelled shifts bypass that.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D110508