[all-commits] [llvm/llvm-project] 5be266: [AArch64][SVE] Improve VECTOR_SPLICE codegen for V...

[Bradley Smith via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5be266db7ab2c16072d1669aaa01c9dfac0dc9bc
      https://github.com/llvm/llvm-project/commit/5be266db7ab2c16072d1669aaa01c9dfac0dc9bc
  Author: Bradley Smith <bradley.smith at arm.com>
  Date:   2021-10-07 (Thu, 07 Oct 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    M llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll

  Log Message:
  -----------
  [AArch64][SVE] Improve VECTOR_SPLICE codegen for VL > 128-bit

Differential Revision: https://reviews.llvm.org/D111135