[all-commits] [llvm/llvm-project] bd4dad: [MachineInstr] Move MIParser's DBG_VALUE RegState:...

[Jack Andersen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bd4dad87f421db82430f9958b52fbccc69d91b16
      https://github.com/llvm/llvm-project/commit/bd4dad87f421db82430f9958b52fbccc69d91b16
  Author: Jack Andersen <jackoalan at gmail.com>
  Date:   2021-10-07 (Thu, 07 Oct 2021)

  Changed paths:
    M llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
    M llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
    M llvm/lib/CodeGen/MIRParser/MIParser.cpp
    M llvm/lib/CodeGen/MachineFunction.cpp
    M llvm/lib/CodeGen/MachineInstr.cpp
    M llvm/lib/CodeGen/MachineOperand.cpp
    M llvm/lib/CodeGen/MachineVerifier.cpp
    M llvm/lib/CodeGen/PrologEpilogInserter.cpp
    M llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
    M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
    M llvm/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp
    M llvm/lib/Target/X86/X86FastISel.cpp
    M llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp
    M llvm/unittests/CodeGen/MachineInstrTest.cpp

  Log Message:
  -----------
  [MachineInstr] Move MIParser's DBG_VALUE RegState::Debug invariant into MachineInstr::addOperand

Based on the reasoning of D53903, register operands of DBG_VALUE are
invariably treated as RegState::Debug operands. This change enforces
this invariant as part of MachineInstr::addOperand so that all passes
emit this flag consistently.

RegState::Debug is inconsistently set on DBG_VALUE registers throughout
LLVM. This runs the risk of a filtering iterator like
MachineRegisterInfo::reg_nodbg_iterator to process these operands
erroneously when not parsed from MIR sources.

This issue was observed in the development of the llvm-mos fork which
adds a backend that relies on physical register operands much more than
existing targets. Physical RegUnit 0 has the same numeric encoding as
$noreg (indicating an undef for DBG_VALUE). Allowing debug operands into
the machine scheduler correlates $noreg with RegUnit 0 (i.e. a collision
of register numbers with different zero semantics). Eventually, this
causes an assert where DBG_VALUE instructions are prohibited from
participating in live register ranges.

Reviewed By: MatzeB, StephenTozer

Differential Revision: https://reviews.llvm.org/D110105