[all-commits] [llvm/llvm-project] 73346f: [ARM] Introduce a MQPRCopy

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 73346f58486d29c0d2687af1208fa146168d62d8
      https://github.com/llvm/llvm-project/commit/73346f58486d29c0d2687af1208fa146168d62d8
  Author: David Green <david.green at arm.com>
  Date:   2021-10-07 (Thu, 07 Oct 2021)

  Changed paths:
    M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
    M llvm/lib/Target/ARM/ARMInstrMVE.td
    M llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/spillingmove.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/spillingmove.mir
    M llvm/unittests/Target/ARM/MachineInstrTest.cpp

  Log Message:
  -----------
  [ARM] Introduce a MQPRCopy

Currently when creating tail predicated loops, we need to validate that
all the live-outs of a loop will be equivalent with and without tail
predication, and if they are not we cannot legally create a
tail-predicated loop, leaving expensive vctp and vpst instructions in
the loop. These notably can include register-allocation instructions
like stack loads and stores, and copys lowered from COPYs to MVE_VORRs.

Instead of trying to prove this is valid late in the pipeline, this
patch introduces a MQPRCopy pseudo instruction that COPY is lowered to.
This can then either be converted to a MVE_VORR where possible, or to a
couple of VMOVD instructions if not. This way they do not behave
differently within and outside of tail-predications regions, and we can
know by construction that they are always valid. The idea is that we can
do the same with stack load and stores, converting them to VLDR/VSTR or
VLDM/VSTM where required to prove tail predication is always valid.

This does unfortunately mean inserting multiple VMOVD instructions,
instead of a single MVE_VORR, but my experiments show it to be an
improvement in general.

Differential Revision: https://reviews.llvm.org/D111048