[all-commits] [llvm/llvm-project] 42ba79: [AArch64][SME] Update tile slice index offset

[Cullen Rhodes via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 42ba79b7b025c97c3aff2b958f18be90e70239f2
      https://github.com/llvm/llvm-project/commit/42ba79b7b025c97c3aff2b958f18be90e70239f2
  Author: Cullen Rhodes <cullen.rhodes at arm.com>
  Date:   2021-10-07 (Thu, 07 Oct 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
    M llvm/lib/Target/AArch64/SMEInstrFormats.td
    M llvm/test/MC/AArch64/SME/ld1b-diagnostics.s
    M llvm/test/MC/AArch64/SME/ld1b.s
    M llvm/test/MC/AArch64/SME/ld1d-diagnostics.s
    M llvm/test/MC/AArch64/SME/ld1d.s
    M llvm/test/MC/AArch64/SME/ld1h-diagnostics.s
    M llvm/test/MC/AArch64/SME/ld1h.s
    M llvm/test/MC/AArch64/SME/ld1q-diagnostics.s
    M llvm/test/MC/AArch64/SME/ld1q.s
    M llvm/test/MC/AArch64/SME/ld1w-diagnostics.s
    M llvm/test/MC/AArch64/SME/ld1w.s
    M llvm/test/MC/AArch64/SME/ldr.s
    M llvm/test/MC/AArch64/SME/mova-diagnostics.s
    M llvm/test/MC/AArch64/SME/mova.s
    M llvm/test/MC/AArch64/SME/st1b-diagnostics.s
    M llvm/test/MC/AArch64/SME/st1b.s
    M llvm/test/MC/AArch64/SME/st1d-diagnostics.s
    M llvm/test/MC/AArch64/SME/st1d.s
    M llvm/test/MC/AArch64/SME/st1h-diagnostics.s
    M llvm/test/MC/AArch64/SME/st1h.s
    M llvm/test/MC/AArch64/SME/st1q-diagnostics.s
    M llvm/test/MC/AArch64/SME/st1q.s
    M llvm/test/MC/AArch64/SME/st1w-diagnostics.s
    M llvm/test/MC/AArch64/SME/st1w.s
    M llvm/test/MC/AArch64/SME/str.s

  Log Message:
  -----------
  [AArch64][SME] Update tile slice index offset

Changes in architecture revision 00eac1:
  * Tile slice index offset no longer prefixed with '#'.
  * The syntax for 128-bit (.Q) ZA tile slice accesses must now include
    an explicit zero index.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-09

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D111212


  Commit: 14cb138b15adafe7d4a1cd7cb2e836c40a5957b5
      https://github.com/llvm/llvm-project/commit/14cb138b15adafe7d4a1cd7cb2e836c40a5957b5
  Author: Cullen Rhodes <cullen.rhodes at arm.com>
  Date:   2021-10-07 (Thu, 07 Oct 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
    M llvm/lib/Target/AArch64/SMEInstrFormats.td
    R llvm/test/MC/AArch64/SME/dup-diagnostics.s
    R llvm/test/MC/AArch64/SME/dup.s
    A llvm/test/MC/AArch64/SME/psel-diagnostics.s
    A llvm/test/MC/AArch64/SME/psel.s

  Log Message:
  -----------
  [AArch64][SME] Update DUP (predicate) instruction

Changes in architecture revision 00eac1:
  * Renamed to PSEL.
  * Copies whole source register.
  * Element type suffix removed from destination.
  * Element index no longer optional and '#' prefix has been removed.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-09

Depends on D111212.

Reviewed By: kmclaughlin

Differential Revision: https://reviews.llvm.org/D111213


Compare: https://github.com/llvm/llvm-project/compare/09fdfd03ea59...14cb138b15ad