[all-commits] [llvm/llvm-project] 80a645: [RISCV] Update to vlm.v and vsm.v according to v1....

[Kai Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 80a645630660b1096aa16e18ed4747b24995f6cb
      https://github.com/llvm/llvm-project/commit/80a645630660b1096aa16e18ed4747b24995f6cb
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-10-05 (Tue, 05 Oct 2021)

  Changed paths:
    M clang/include/clang/Basic/riscv_vector.td
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vse.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
    M llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
    M llvm/test/CodeGen/RISCV/rvv/load-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll
    M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
    R llvm/test/CodeGen/RISCV/rvv/vle1-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vle1-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vlm-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vlm-rv64.ll
    R llvm/test/CodeGen/RISCV/rvv/vse1-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vse1-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vsm-rv32.ll
    A llvm/test/CodeGen/RISCV/rvv/vsm-rv64.ll
    M llvm/test/MC/RISCV/rvv/aliases.s
    M llvm/test/MC/RISCV/rvv/load.s
    M llvm/test/MC/RISCV/rvv/store.s

  Log Message:
  -----------
  [RISCV] Update to vlm.v and vsm.v according to v1.0-rc1.

vle1.v  -> vlm.v
vse1.v  -> vsm.v

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D106044