[all-commits] [llvm/llvm-project] 33d209: Revert "[RISCV] Add an GPR def to the Zvlseg SPILL...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 33d20977b7a64d5fe09072fabe1f3349d422555d
      https://github.com/llvm/llvm-project/commit/33d20977b7a64d5fe09072fabe1f3349d422555d
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-10-02 (Sat, 02 Oct 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir

  Log Message:
  -----------
  Revert "[RISCV] Add an GPR def to the Zvlseg SPILL/RELOAD pseudos"

This reverts commit 1f161919065fbfa2b39b8f373553a64b89f826f8.

We're seeing some issues with this internally. It seems that when
the spill is created by register allocation, the GPR doesn't get
allocated and an assertion fires during virtual register rewriting.

The .mir test case contains the spill before register allocation so
register allocation sees it as any other instruction.