[all-commits] [llvm/llvm-project] 72a08c: [VP] Vector predicated vector splice intrinsic

[Simon Moll via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 72a08c0b940450424b4c5d5babfb374df14ef471
      https://github.com/llvm/llvm-project/commit/72a08c0b940450424b4c5d5babfb374df14ef471
  Author: Simon Moll <simon.moll at emea.nec.com>
  Date:   2021-09-29 (Wed, 29 Sep 2021)

  Changed paths:
    M llvm/docs/LangRef.rst
    M llvm/include/llvm/IR/Intrinsics.td
    M llvm/include/llvm/IR/VPIntrinsics.def
    M llvm/test/Verifier/vp-intrinsics.ll
    M llvm/unittests/IR/VPIntrinsicTest.cpp

  Log Message:
  -----------
  [VP] Vector predicated vector splice intrinsic

This patch introduces the vector-predicated version of the
experimental_vector_splice intrinsic [1] at the IR level. It considers
the active vector length for both vectors and and uses a vector mask to
disable certain lanes in the result.

[1] https://reviews.llvm.org/D94708

Change originally authored by Vineet Kumar <vineet.kumar at bsc.es>

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D103898