[all-commits] [llvm/llvm-project] 7255ce: [SelectionDAG] Fix incorrect condition for shift a...

[nextsilicon-itay-bookstein via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7255ce30e48feb07e4e82613f518683fbc247c1c
      https://github.com/llvm/llvm-project/commit/7255ce30e48feb07e4e82613f518683fbc247c1c
  Author: Itay Bookstein <itay.bookstein at nextsilicon.com>
  Date:   2021-09-28 (Tue, 28 Sep 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

  Log Message:
  -----------
  [SelectionDAG] Fix incorrect condition for shift amount truncation

Comment says:
  // If the operand is larger than the shift count type but the shift
  // count type has enough bits to represent any shift value ...

It clearly talks about the shifted operand, not the shift-amount operand,
but the comparison is performed against Log2_32_Ceil(Op2.getValueSizeInBits())
where Op2 is the shift amount operand. This comparison also doesn't make
sense in the context of the previous one (ShiftsSize > Op2Size) because
Op2Size == Op2.getValueSizeInBits(). Fix to use Op1.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D110509