[all-commits] [llvm/llvm-project] aa93c5: [X86][Costmodel] Load/store i16 Stride=6 VF=2 inte...

[Roman Lebedev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: aa93c55889ec6284e0337d6baf01c71dadd76043
      https://github.com/llvm/llvm-project/commit/aa93c55889ec6284e0337d6baf01c71dadd76043
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2021-09-28 (Tue, 28 Sep 2021)

  Changed paths:
    M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-6.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-6.ll

  Log Message:
  -----------
  [X86][Costmodel] Load/store i16 Stride=6 VF=2 interleaving costs

The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3

For load we have:
https://godbolt.org/z/bhscej4WM - for intels `Block RThroughput: =13.0`; for ryzens, `Block RThroughput: <=7.0`
So pick cost of `13`.

For store we have:
https://godbolt.org/z/Yf4Pfnxbq - for intels `Block RThroughput: =10.0`; for ryzens, `Block RThroughput: <=3.5`
So pick cost of `10`.

I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D110590


  Commit: b3011bcc78926686dd95bd5dbb4c2c66d8be24a2
      https://github.com/llvm/llvm-project/commit/b3011bcc78926686dd95bd5dbb4c2c66d8be24a2
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2021-09-28 (Tue, 28 Sep 2021)

  Changed paths:
    M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-6.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-6.ll

  Log Message:
  -----------
  [X86][Costmodel] Load/store i16 Stride=6 VF=4 interleaving costs

The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3

For load we have:
https://godbolt.org/z/1Wcaf9c7T - for intels `Block RThroughput: =9.0`; for ryzens, `Block RThroughput: <=4.5`
So pick cost of `9`.

For store we have:
https://godbolt.org/z/1Wcaf9c7T - for intels `Block RThroughput: =15.0`; for ryzens, `Block RThroughput: <=6.0`
So pick cost of `15`.

I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D110591


  Commit: 24e42f7d28e98152484cf9bbf8ee4080f5082da0
      https://github.com/llvm/llvm-project/commit/24e42f7d28e98152484cf9bbf8ee4080f5082da0
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2021-09-28 (Tue, 28 Sep 2021)

  Changed paths:
    M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-6.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-6.ll

  Log Message:
  -----------
  [X86][Costmodel] Load/store i16 Stride=6 VF=8 interleaving costs

The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3

For load we have:
https://godbolt.org/z/3Tc5s897j - for intels `Block RThroughput: =39.0`; for ryzens, `Block RThroughput: <=13.5`
So pick cost of `39`.

For store we have:
https://godbolt.org/z/fo1h9E67e - for intels `Block RThroughput: =21.0`; for ryzens, `Block RThroughput: <=12.0`
So pick cost of `21`.

I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D110592


  Commit: b6b7860954c677003a5a0b0d4071e88aa44e9081
      https://github.com/llvm/llvm-project/commit/b6b7860954c677003a5a0b0d4071e88aa44e9081
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2021-09-28 (Tue, 28 Sep 2021)

  Changed paths:
    M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-6.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-6.ll

  Log Message:
  -----------
  [X86][Costmodel] Load/store i16 Stride=6 VF=16 interleaving costs

The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3

For this tuple, measuring becomes problematic since there's a lot of spilling going on,
but apparently all these memory ops do not affect worst-case estimate at all here.

For load we have:
https://godbolt.org/z/5qGb9odP6 - for intels `Block RThroughput: <=106.0`; for ryzens, `Block RThroughput: <=34.8`
So pick cost of `106`.

For store we have:
https://godbolt.org/z/KrWcv4Ph7 - for intels `Block RThroughput: =58.0`; for ryzens, `Block RThroughput: <=20.5`
So pick cost of `58`.

I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D110593


Compare: https://github.com/llvm/llvm-project/compare/ce40843a3fe1...b6b7860954c6