[all-commits] [llvm/llvm-project] 73a196: Recommit "[AArch64] Split bitmask immediate of bit...

[JinGu Kang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 73a196a11c0e6fe7bbf33055cc2c96ce3c61ff0d
      https://github.com/llvm/llvm-project/commit/73a196a11c0e6fe7bbf33055cc2c96ce3c61ff0d
  Author: Jingu Kang <jingu.kang at arm.com>
  Date:   2021-09-28 (Tue, 28 Sep 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64.h
    A llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
    M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
    M llvm/lib/Target/AArch64/CMakeLists.txt
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h
    M llvm/test/CodeGen/AArch64/O3-pipeline.ll
    A llvm/test/CodeGen/AArch64/aarch64-split-and-bitmask-immediate.ll
    M llvm/test/CodeGen/AArch64/unfold-masked-merge-scalar-constmask-innerouter.ll

  Log Message:
  -----------
  Recommit "[AArch64] Split bitmask immediate of bitwise AND operation"

This reverts the revert commit f85d8a5bed95cc17a452b6b63b9866fbf181d94d
with bug fixes.

Original message:

    MOVi32imm + ANDWrr ==> ANDWri + ANDWri
    MOVi64imm + ANDXrr ==> ANDXri + ANDXri

    The mov pseudo instruction could be expanded to multiple mov instructions later.
    In this case, try to split the constant operand of mov instruction into two
    bitmask immediates. It makes only two AND instructions intead of multiple
    mov + and instructions.

    Added a peephole optimization pass on MIR level to implement it.

    Differential Revision: https://reviews.llvm.org/D109963