[all-commits] [llvm/llvm-project] 864b20: [AArch64] Split bitmask immediate of bitwise AND o...

[JinGu Kang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 864b206796ae8aa7f35f830655337751dbd9176c
      https://github.com/llvm/llvm-project/commit/864b206796ae8aa7f35f830655337751dbd9176c
  Author: Jingu Kang <jingu.kang at arm.com>
  Date:   2021-09-28 (Tue, 28 Sep 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64.h
    A llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
    M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
    M llvm/lib/Target/AArch64/CMakeLists.txt
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h
    M llvm/test/CodeGen/AArch64/O3-pipeline.ll
    A llvm/test/CodeGen/AArch64/aarch64-split-and-bitmask-immediate.ll
    M llvm/test/CodeGen/AArch64/unfold-masked-merge-scalar-constmask-innerouter.ll

  Log Message:
  -----------
  [AArch64] Split bitmask immediate of bitwise AND operation

MOVi32imm + ANDWrr ==> ANDWri + ANDWri
MOVi64imm + ANDXrr ==> ANDXri + ANDXri

The mov pseudo instruction could be expanded to multiple mov instructions later.
In this case, try to split the constant operand of mov instruction into two
bitmask immediates. It makes only two AND instructions intead of multiple
mov + and instructions.

Added a peephole optimization pass on MIR level to implement it.

Differential Revision: https://reviews.llvm.org/D109963