[all-commits] [llvm/llvm-project] a2a07e: [RISCV] Fold store of vmv.x.s to a vse with VL=1.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a2a07e8db3bf64440f24d9d6408df214886826de
      https://github.com/llvm/llvm-project/commit/a2a07e8db3bf64440f24d9d6408df214886826de
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-09-27 (Mon, 27 Sep 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/SelectionDAG.h
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
    M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll

  Log Message:
  -----------
  [RISCV] Fold store of vmv.x.s to a vse with VL=1.

This can avoid a loss of decoupling with the scalar unit on cores
with decoupled scalar and vector units.

We should support FP too, but those use extract_element and not a
custom ISD node so it is a little different. I also left a FIXME
in the test for i64 extract and store on RV32.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D109482