[all-commits] [llvm/llvm-project] 354ded: tsan: align ThreadState to cache line

[Dmitry Vyukov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 354ded67b30d0f8115dde2f0bbed260d6f4d1b3d
      https://github.com/llvm/llvm-project/commit/354ded67b30d0f8115dde2f0bbed260d6f4d1b3d
  Author: Dmitry Vyukov <dvyukov at google.com>
  Date:   2021-09-27 (Mon, 27 Sep 2021)

  Changed paths:
    M compiler-rt/lib/tsan/rtl/tsan_rtl.cpp
    M compiler-rt/lib/tsan/rtl/tsan_rtl.h

  Log Message:
  -----------
  tsan: align ThreadState to cache line

There are 2 reasons to do this:
1. We place hot data in the first cache line of ThreadState,
this assumed that it's cache-line-aligned but we never actually
enforced it (or it was lost at some point).
2. The new vector clock uses vector instructions and requires
data alignment. Later the new vector clock will be embedded in
ThreadState, then ensuring vector clock alignment will be
impossible w/o ThreadState alignment.

Depends on D110519.

Reviewed By: melver

Differential Revision: https://reviews.llvm.org/D110520