[all-commits] [llvm/llvm-project] d9413f: [X86][Costmodel] Load/store i16 VF=2 interleaving ...

[Roman Lebedev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d9413f46b308df5afd7fc106df2af809757bb0c9
      https://github.com/llvm/llvm-project/commit/d9413f46b308df5afd7fc106df2af809757bb0c9
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2021-09-26 (Sun, 26 Sep 2021)

  Changed paths:
    M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-2.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-2.ll

  Log Message:
  -----------
  [X86][Costmodel] Load/store i16 VF=2 interleaving costs

The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3

For load we have:
https://godbolt.org/z/M8vEKs5jY - for intels `Block RThroughput: =2.0`;
                                  for ryzens, `Block RThroughput: <=1.0`
So pick cost of `2`.

For store we have:
https://godbolt.org/z/Kx1nKz7je - for intels `Block RThroughput: =1.0`;
                                  for ryzens, `Block RThroughput: <=0.5`
So pick cost of `1`.

I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D103144