[all-commits] [llvm/llvm-project] 2a4fa0: [X86][SSE] combineMulToPMADDWD - enable sext(v8i16...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2a4fa0c27c938b9767dd42d57cc7c4e5a670b302
      https://github.com/llvm/llvm-project/commit/2a4fa0c27c938b9767dd42d57cc7c4e5a670b302
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2021-09-25 (Sat, 25 Sep 2021)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/shrink_vmul.ll

  Log Message:
  -----------
  [X86][SSE] combineMulToPMADDWD - enable sext(v8i16) -> zext(v8i16) fold on sub-128 bit vectors


  Commit: eb7c78c2c5223b60e1f4f03876beceb46c26dd48
      https://github.com/llvm/llvm-project/commit/eb7c78c2c5223b60e1f4f03876beceb46c26dd48
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2021-09-25 (Sat, 25 Sep 2021)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/shrink_vmul.ll

  Log Message:
  -----------
  [X86][SSE] combineMulToPMADDWD - mask off upper bits of sign-extended vXi32 constants

If we are multiplying by a sign-extended vXi32 constant, then we can mask off the upper 16 bits to allow folding to PMADDWD and make use of its implicit sign-extension from i16


Compare: https://github.com/llvm/llvm-project/compare/44c401bdc355...eb7c78c2c522